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14-bit, 170 msps/210 msps/250 msps, 1.8 v dual analog-to-digital converter ( adc) AD9643 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features snr = 70.6 dbfs at 185 mhz a in and 250 msps sfdr = 85 dbc at 185 mhz a in and 250 msps ?151.6 dbfs/hz input noise at 185 mhz, ?1 dbfs a in and 250 msps total power consumption: 785 mw at 250 msps 1.8 v supply voltages lvds (ansi-644 levels) outputs integer 1-to-8 input clock divider (625 mhz maximum input) sample rates of up to 250 msps if sampling frequencies of up to 400 mhz internal adc voltage reference flexible analog input range 1.4 v p-p to 2.0 v p-p (1.75 v p-p nominal) adc clock duty cycle stabilizer 95 db channel isolation/crosstalk serial port control energy saving power-down modes user-configurable, built-in self-test (bist) capability applications communications diversity radio systems multimode digital receivers (3g) td-scdma, wimax, wcdma, cdma2000, gsm, edge, lte i/q demodulation systems smart antenna systems general-purpose software radios ultrasound equipment broadband data applications functional block diagram 14 14 reference serial port sclk sdio csb clk+ clk? sync 1to 8 clock divider AD9643 vin+a d0 d13 dco or pdwn oeb vin?a v in+b vcm vin?b notes 1. the d0 to d13 pins represent both the channel a and channe l b lvds output data. a v dd agnd dr v dd 09636-001 . . . . . parallel ddr lvds and drivers pipeline 14-bit adc pipeline 14-bit adc figure 1. general description the AD9643 is a dual, 14-bit analog-to-digital converter (adc) with sampling speeds of up to 250 msps. the AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. the dual adc cores feature a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth inputs supporting a variety of user-selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer is provided to compensate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. the adc output data is routed directly to the two external 14-bit lvds output ports and formatted as either interleaved or channel multiplexed. flexible power-down options allow significant power savings, when desired. programming for setup and control are accomplished using a 3-wire spi-compatible serial interface. the AD9643 is available in a 64-lead lfcsp and is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. integrated dual, 14-bit, 170 msps/210 msps/250 msps adcs. 2. operation from a single 1.8 v supply and a separate digital output driver supply accommodating lvds outputs. 3. proprietary differential input maintains excellent snr performance for input frequencies of up to 400 mhz. 4. sync input allows synchronization of multiple devices. 5. 3-pin, 1.8 v spi port for register programming and register readback. 6. pin compatibility with the ad9613 , allowing a simple migration down from 14 bits to 12 bits. this part is also pin compatible with the ad6649 and the ad6643 . www..net
AD9643 rev. a | page 2 of 36 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? adc dc specifications ............................................................... 3 ? adc ac specifications ............................................................... 4 ? digital specifications ................................................................... 6 ? switching specifications .............................................................. 8 ? timing specifications .................................................................. 9 ? absolute maximum ratings .......................................................... 11 ? thermal characteristics ............................................................ 11 ? esd caution ................................................................................ 11 ? pin configurations and function descriptions ......................... 12 ? typical performance characteristics ........................................... 16 ? equivalent circuits ......................................................................... 22 ? theory of operation ...................................................................... 23 ? adc architecture ...................................................................... 23 ? analog input considerations ................................................... 23 ? voltage reference ....................................................................... 25 ? clock input considerations ...................................................... 25 ? power dissipation and standby mode .................................... 26 ? digital outputs ........................................................................... 27 ? channel/chip synchronization .................................................... 28 ? serial port interface (spi) .............................................................. 29 ? configuration using the spi ..................................................... 29 ? hardware interface ..................................................................... 29 ? spi accessible features .............................................................. 30 ? memory map .................................................................................. 31 ? reading the memory map register table ............................... 31 ? memory map register table ..................................................... 32 ? memory map register description ......................................... 34 ? applications information .............................................................. 35 ? design guidelines ...................................................................... 35 ? outline dimensions ....................................................................... 36 ? ordering guide .......................................................................... 36 ? revision history 5/11rev. 0 to rev. a changes to table 2, worst other (harmonic or spur) max values ......................................................................................... 4 4/11revision 0: initial version
AD9643 rev. a | page 3 of 36 specifications adc dc specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.75 v p-p full-scale input range, duty cycle stabilizer (dcs) enabled, unless otherwise noted. table 1. AD9643-170 AD9643-210 AD9643-250 parameter temperature min typ max min typ max min typ max unit resolution full 14 14 14 bits accuracy no missing codes full guaranteed guaranteed guaranteed offset error full 10 10 10 mv gain error full +2/?6 +3/?5 4 %fsr differential nonlinearity (dnl) full 0.75 0.75 0.75 lsb 25c 0.25 0.25 0.25 lsb integral nonlinearity (inl) 1 full 1.8 2 3.5 lsb 25c 1.5 1.5 1.5 lsb matching characteristic offset error full 13 13 13 mv gain error full 2.5/ +3.5 ?2/ +3.5 ?2.5/ +3.5 %fsr temperature drift offset error full 15 15 15 ppm/c gain error full 50 50 50 ppm/c input referred noise vref = 1.0 v 25c 1.33 1.33 1.33 lsb rms analog input input span full 1.75 1.75 1.75 v p-p input capacitance 2 full 2.5 2.5 2.5 pf input resistance 3 full 20 20 20 k input common-mode voltage full 0.9 0.9 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 1. 7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1. 7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd 1 full 196 250 217 265 256 275 ma i drvdd 1 full 145 160 160 185 180 210 ma power consumption sine wave input (drvdd = 1.8 v) full 614 680 785 mw standby power 4 full 90 90 90 mw power-down power full 10 10 10 mw 1 measured with a low input frequency, full-scale sine wave. 2 input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 standby power is measured with a dc input and the clk pin inactive (that is, set to avdd or agnd).
AD9643 rev. a | page 4 of 36 adc ac specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.75 v p-p full-scale input range, unless otherwise noted. table 2. AD9643-170 AD9643-210 AD9643-250 parameter 1 temperature min typ max min typ max min typ max unit signal-to-noise-ratio (snr) f in = 30 mhz 25c 72.2 72.2 72.0 dbfs f in = 90 mhz 25c 72.0 72.0 71.7 dbfs full 70.4 69.9 dbfs f in = 140 mhz 25c 71.8 71.6 71.4 dbfs f in = 185 mhz 25c 71.4 71.2 70.9 dbfs full 68.8 dbfs f in = 220 mhz 25c 71.1 70.9 70.5 dbfs signal-to-noise and distortion (sinad) f in = 30 mhz 25c 71.2 71.2 71.0 dbfs f in = 90 mhz 25c 71.0 71.0 70.7 dbfs full 70.4 69.9 dbfs f in = 140 mhz 25c 70.8 70.6 70.4 dbfs f in = 185 mhz 25c 70.4 70.2 69.9 dbfs full 67.5 dbfs f in = 220 mhz 25c 70.1 69.9 69.5 dbfs effective number of bits (enob) f in = 30 mhz 25c 11.5 11.5 11.5 bits f in = 90 mhz 25c 11.5 11.5 11.5 bits f in = 140 mhz 25c 11.5 11.5 11.4 bits f in = 185 mhz 25c 11.4 11.4 11.3 bits f in = 220 mhz 25c 11.4 11.3 11.3 bits worst second or third harmonic f in = 30 mhz 25c ?95 ?90 ?90 dbc f in = 90 mhz 25c ?92 ?90 ?88 dbc full ?78 ?80 dbc f in = 140 mhz 25c ?88 ?88 ?85 dbc f in = 185 mhz 25c ?83 ?87 ?85 dbc full ?80 dbc f in = 220 mhz 25c ?83 ?85 ?85 dbc spurious-free dynamic range (sfdr) f in = 30 mhz 25c 95 90 90 dbc f in = 90 mhz 25c 92 90 88 dbc full 78 80 dbc f in = 140 mhz 25c 88 88 86 dbc f in = 185 mhz 25c 83 87 85 dbc full 80 dbc f in = 220 mhz 25c 83 85 85 dbc worst other (harmonic or spur) f in = 30 mhz 25c ?98 ?95 ?94 dbc f in = 90 mhz 25c ?97 ?95 ?93 dbc full ?78 ?80 dbc f in = 140 mhz 25c ?97 ?93 ?92 dbc f in = 185 mhz 25c ?96 ?92 ?92 dbc full ?80 dbc f in = 220 mhz 25c ?94 ?90 ?88 dbc two-tone sfdr f in = 184.12 mhz (?7 dbfs ), 187.12 mhz (?7 dbfs ) 25c 88 88 88 dbc
AD9643 rev. a | page 5 of 36 AD9643-170 AD9643-210 AD9643-250 parameter 1 temperature min typ max min typ max min typ max unit crosstalk 2 full 95 95 95 db full power bandwidth 3 25c 400 400 400 mhz noise bandwidth 4 25c 1000 1000 1000 mhz 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1.0 dbfs on one channel an d no input on the alternate channel. 3 full power bandwidth is the bandwidth of operation in which proper adc performance can be achieved. 4 noise bandwidth is the ?3 db bandwidth for the adc inputs across which noise can enter the adc and is not attenuated internall y.
AD9643 rev. a | page 6 of 36 digital specifications avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.75 v p-p full-scale input range, dcs enabled, unless otherwise noted. table 3. parameter temp min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage full 0.3 3.6 v p-p input voltage range full agnd avdd v input common-mode range full 0.9 1.4 v high level input current full ?10 +22 a low level input current full ?22 ?10 a input capacitance full 4 pf input resistance full 8 10 12 k sync input logic compliance cmos/lvds internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ?5 +5 a low level input current full ?5 +5 a input capacitance full 1 pf input resistance full 12 16 20 k logic input (csb) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?5 +5 a low level input current full ?80 ?45 a input resistance full 26 k input capacitance full 2 pf logic input (sclk) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k input capacitance full 2 pf logic inputs (sdio) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k input capacitance full 5 pf logic inputs (oeb, pdwn) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k input capacitance full 5 pf
AD9643 rev. a | page 7 of 36 parameter temp min typ max unit digital outputs lvds data and or outputs differential output voltage (vod), ansi mode full 250 350 450 mv output offset voltage (vos), ansi mode full 1.15 1.25 1.35 v differential output voltage (vod), reduced swing mode full 150 200 280 mv output offset voltage (vos), reduced swing mode full 1.15 1.25 1.35 v 1 pull-up. 2 pull-down.
AD9643 rev. a | page 8 of 36 switching specifications table 4. AD9643-170 AD9643-210 AD9643-250 parameter temp min typ max max typ max min typ max unit clock input parameters input clock rate full 625 625 625 mhz conversion rate 1 full 40 170 40 210 40 250 msps clk perioddivide-by-1 mode (t clk ) full 5.8 4.8 4 ns clk pulse width high (t ch ) divide-by-1 mode, dcs enabled full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns divide-by-1 mode, dcs disabled full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns divide-by-2 mode through divide-by-8 mode full 0.8 0.8 0.8 ns aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 0.1 ps rms data output parameters lvds mode data propagation delay (t pd ) full 4.8 4.8 4.8 ns dco propagation delay (t dco ) full 5.5 5.5 5.5 ns dco-to-data skew (t skew ) full 0.1 0.7 1.3 0.1 0.7 1.3 0.1 0.7 1.3 ns pipeline delay (latency) full 10 10 10 cycles aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 0.1 ps rms wake-up time (from standby) full 10 10 10 s wake-up time (from power-down) full 250 250 250 s out-of-range recovery time full 3 3 3 cycles 1 conversion rate is the clock rate after the divider.
AD9643 rev. a | page 9 of 36 timing specifications table 5. parameter conditions min typ max unit sync timing requirements t ssync sync to the rising edge of clk setup time 0.3 ns t hsync sync to the rising edge of clk hold time 0.4 ns spi timing requirements t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk should be in a logic high state 10 ns t low minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns
AD9643 rev. a | page 10 of 36 timing diagrams vin clk+ clk? dco? dco+ d0 (lsb) parallel interleaved channel multiplexed (even/odd) mode channel multiplexed (even/odd) mode d13 (msb) d0/d1 (lsb) ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch b n ? 8 ch a n ? 7 ch b n ? 7 ch a n ? 6 ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch b n ? 8 ch a n ? 7 ch b n ? 7 ch a n ? 6 ch a0 n ? 10 ch a1 n ? 10 ch a0 n ? 9 ch a1 n ? 9 ch a0 n ? 8 ch a1 n ? 8 ch a0 n ? 7 ch a1 n ? 7 ch a0 n ? 6 ch a12 n ? 10 ch a13 n ? 10 ch a12 n ? 9 ch a13 n ? 9 ch a12 n ? 8 ch a13 n ? 8 ch a12 n ? 7 ch a13 n ? 7 ch a12 n ? 6 ch b0 n ? 10 ch b1 n ? 10 ch b0 n ? 9 ch b1 n ? 9 ch b0 n ? 8 ch b1 n ? 8 ch b0 n ? 7 ch b1 n ? 7 ch b0 n ? 6 ch b12 n ? 10 ch b13 n ? 10 ch b12 n ? 9 ch b13 n ? 9 ch b12 n ? 8 ch b13 n ? 8 ch b12 n ? 7 ch b13 n ? 7 ch b12 n ? 6 channel a d12/d13 (msb) d0/d1 (lsb) channel b d12/d13 (msb) n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 t a t ch t pd t skew t dco t clk 09636-002 . . . . . . . . . channel a and channel b figure 2. lvds modes for data output timing t ssync t hsync sync clk+ 09636-003 figure 3. sync timing inputs
AD9643 rev. a | page 11 of 36 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v vin+a/vin+b, vin?a/vin?b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v sync to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to drvdd + 0.3 v sclk to agnd ?0.3 v to drvdd + 0.3 v sdio to agnd ?0.3 v to drvdd + 0.3 v oeb to agnd ?0.3 v to drvdd + 0.3 v pdwn to agnd ?0.3 v to drvdd + 0.3 v or+/or? to agnd ?0.3 v to drvdd + 0.3 v d0?/d0+ through d13?/d13+ to agnd ?0.3 v to drvdd + 0.3 v dco+/dco? to agnd ?0.3 v to drvdd + 0.3 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. this increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7. thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 unit 0 26.8 1.14 10.4 c/w 1.0 21.6 c/w 64-lead lfcsp 9 mm 9 mm (cp-64-4) 2.0 20.2 c/w 1 per jedec 51-7, plus jede c 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). typical ja is specified for a 4-layer pcb with a solid ground plane. as shown in table 7 , airflow increases heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the ja . esd caution
AD9643 rev. a | page 12 of 36 pin configurations and function descriptions 09636-004 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d4? d4+ drvdd d5? d5+ d6? d6+ dco? dco+ d7? d7+ drvdd d8? d8+ d9? d9+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+ a avdd avdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk+ clk? sync dnc dnc dnc dnc (lsb) d0? (lsb) d0+ drvdd d1? d1+ d2? d2+ d3? d3+ notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio or+ or? d13+ (msb) d13? (msb) d12+ d12? drvdd d11+ d11? d10+ d10? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9643 parallel lvds top view (not to scale) pin 1 indicator figure 4. lfcsp interleaved parallel lvds pin configuration (top view) table 8. pin function descriptions for interleaved parallel lvds mode pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital o utput driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4, 5, 6, 7, 55, 56, 58 dnc do not connect. do not connect to this pin. 0 agnd, exposed paddle ground analog ground. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin?a input differential analog input pin (?) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin?b input differential analog input pin (?) for channel b. 57 vcm output common-mode level bias output for analog inputs. this pin should be decoupled to ground using a 0.1 f capacitor. 1 clk+ input adc clock inputtrue. 2 clk? input adc clock inputcomplement. digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 9 d0+ (lsb) output channel a/channel b lvds output data 0true. 8 d0? (lsb) output channel a/channel b lvds output data 0complement. 12 d1+ output channel a/channel b lvds output data 1true. 11 d1? output channel a/channel b lvds output data 1complement. 14 d2+ output channel a/channel b lvds output data 2true. 13 d2? output channel a/channel b lvds output data 2complement. 16 d3+ output channel a/channel b lvds output data 3true. 15 d3? output channel a/channel b lvds output data 3complement. 18 d4+ output channel a/channel b lvds output data 4true.
AD9643 rev. a | page 13 of 36 pin no. mnemonic type description 17 d4? output channel a/channel b lvds output data 4complement. 21 d5+ output channel a/channel b lvds output data 5true. 20 d5? output channel a/channel b lvds output data 5complement. 23 d6+ output channel a/channel b lvds output data 6true. 22 d6? output channel a/channel b lvds output data 6complement. 27 d7+ output channel a/channel b lvds output data 7true. 26 d7? output channel a/channel b lvds output data 7complement. 30 d8+ output channel a/channel b lvds output data 8true. 29 d8? output channel a/channel b lvds output data 8complement. 32 d9+ output channel a/channel b lvds output data 9true. 31 d9? output channel a/channel b lvds output data 9complement. 34 d10+ output channel a/channel b lvds output data 10true. 33 d10? output channel a/channel b lvds output data 10complement. 36 d11+ output channel a/channel b lvds output data 11true. 35 d11? output channel a/channel b lvds output data 11complement. 39 d12+ output channel a/channel b lvds output data 12true. 38 d12? output channel a/channel b lvds output data 12complement. 41 d13+ (msb) output channel a/channel b lvds output data 13true. 40 d13? (msb) output channel a/channe l b lvds output data 13complement. 43 or+ output channel a/channe l b lvds overrangetrue. 42 or? output channel a/channel b lvds overrangecomplement. 25 dco+ output channel a/channel b lvds data clock outputtrue. 24 dco? output channel a/channel b lv ds data clock outputcomplement. spi control 45 sclk input spi serial clock. 44 sdio input/output spi serial data i/o. 46 csb input spi chip select (active low). output enable and power-down 47 oeb input/output output enable input (active low). 48 pdwn input/output power-down input (active high). the operation of this pin depends on the spi mode and can be configured as power-down or standby (see table 14 ).
AD9643 rev. a | page 14 of 36 09636-005 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 b d8?/d9? b d8+/d9+ drvdd b d10?/d11? b d10+/d11+ (msb) b d12?/d13? (msb) b d12+/d13+ dco? dco+ (lsb) a d0?/d1? (lsb) a d0+/d1+ drvdd a d2?/d3? a d2+/d3+ a d4?/d5? a d4+/d5+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+ a avdd avdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk+ clk? sync dnc dnc dnc dnc (lsb) b d0?/d1? (lsb) b d0+/d1+ drvdd b d2?/d3? b d2+/d3+ b d4?/d5? b d4+/d5+ b d6?/d7? b d6+/d7+ notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio or+ or? a d12+/d13+ (msb) a d12?/d13? (msb) a d10+/d11+ a d10?/d11? drvdd a d8+/d9+ a d8?/d9? a d6+/d7+ a d6?/d7? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9643 channel multiplexed (even/odd) lvds top view (not to scale) pin 1 indicator figure 5. lfcsp channel multiplexed (even/odd) lvds pin configuration (top view) table 9. pin function descriptions for channel multiplexed (even/odd) lvds mode pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital o utput driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4, 5, 6, 7 dnc do not connect. do not connect to this pin. 0 agnd, exposed paddle ground analog ground. the exposed thermal paddle on the bottom of the package provides the analog grou nd for the part. this exposed paddle must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin?a input differential analog input pin (?) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin?b input differential analog input pin (?) for channel b. 55 dnc do not connect. do not connect to this pin. 56 dnc do not connect. do not connect to this pin. 58 dnc do not connect. do not connect to this pin. 57 vcm output common-mode level bias output for analog inputs. this pin should be decoupled to ground using a 0.1 f capacitor. 1 clk+ input adc clock inputtrue. 2 clk? input adc clock inputcomplement. digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 8 b d0?/d1? (lsb) output channel b lvds output data 0/data 1complement. 9 b d0+/d1+ (lsb) output channel b lvds output data 0/data 1true. 11 b d2?/d3? output channel b lvds output data 2/data 3complement. 12 b d2+/d3+ output channel b lvds output data 2/data 3true. 13 b d4?/d5? output channel b lvds output data 4/data 5complement.
AD9643 rev. a | page 15 of 36 pin no. mnemonic type description 14 b d4+/d5+ output channel b lvds output data 4/data 5true. 15 b d6?/d7? output channel b lvds output data 6/data 7complement. 16 b d6+/d7+ output channel b lvds output data 6/data 7true. 17 b d8?/d9? output channel b lvds output data 8/data 9complement. 18 b d8+/d9+ output channel b lvds output data 8/data 9true. 20 b d10?/d11? output channel b lvds output data 10/data 11complement. 21 b d10+/d11+ output channel b lv ds output data 10/data 11true. 22 b d12?/d13? (msb) output channel b lvds output data 12/data 13complement. 23 b d12+/d13+ (msb) output channel b lvds output data 12/data 13true. 26 a d0?/d1? (lsb) output channel a lvds output data 0/data 1complement. 27 a d0+/d1+ (lsb) output channel a lvds output data 0/data 1true. 29 a d2?/d3? output channel a lvds output data 2/data 3complement. 30 a d2+/d3+ output channel a lvds output data 2/data 3true. 31 a d4?/d5? output channel a lvds output data 4/data 5complement. 32 a d4+/d5+ output channel a lvds output data 4/data 5true. 33 a d6?/d7? output channel a lvds output data 6/data 7complement. 34 a d6+/d7+ output channel a lvds output data 6/data 7true. 35 a d8?/d9? output channel a lvds output data 8/data 9complement. 36 a d8+/d9+ output channel a lvds output data 8/data 9true. 38 a d10?/d11? output channel a lvds output data 10/data 11complement. 39 a d10+/d11+ output channel a lvds output data 10/data 11true. 40 a d12?/d13? (msb) output channel a lvds output data 12/data 13complement. 41 a d12+/d13+ (msb) output channel a lvds output data 12/data 13true. 43 or+ output channel a/channel b lvds overrange outputtrue. 42 or? output channel a/channel b lvds overrange outputcomplement. 25 dco+ output channel a/channel b lvds data clock outputtrue. 24 dco? output channel a/channel b lv ds data clock outputcomplement. spi control 45 sclk input spi serial clock. 44 sdio input/output spi se rial data input/output. 46 csb input spi chip select (active low). output enable and power-down 47 oeb input output enable input (active low). 48 pdwn input power-down input (active high). the operation of this pin depends on the spi mode and can be configured as power- down or standby (see table 14 ).
AD9643 rev. a | page 16 of 36 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, sample rate = 250 msps, dcs enabled, 1.75 v p-p differential input, vin = ?1.0 dbfs, 32k sample, t a = 25c, unless otherwise noted. 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20304050607080 frequency (mhz) amplitude (dbfs) 09636-013 170msps 90.1mhz @ ?1dbfs snr = 70.8db (71.8dbfs) sfdr = 88dbc figure 6. AD9643-170 single-tone fft with f in = 90.1 mhz 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20304050607080 frequency (mhz) amplitude (dbfs) 09636-014 170msps 185.1mhz @ ?1dbfs snr = 69.8db (70.8dbfs) sfdr = 85dbc figure 7. AD9643-170 single-tone fft with f in = 185.1 mhz 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 02 03 04 05 06 07 08 0 frequency (mhz) amplitude (dbfs) 09636-015 170msps 305.1mhz @ ?1dbfs snr = 68.3db (69.3dbfs) sfdr = 79dbc figure 8. AD9643-170 single-tone fft with f in = 305.1 mhz 120 100 80 60 40 20 0 ?10 ?20?30 ?40?50?60?70?80?90?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09636-016 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 9. AD9643-170 single-tone snr/sfdr vs. input amplitude (a in ) with f in = 90.1 mhz 100 95 90 85 80 75 70 65 60 330 360 390 300270240210180 150 1209060 frequency (mhz) snr/sfdr (dbc and dbfs) 09636-017 snr (dbfs) sfdr (dbc) figure 10. AD9643-170 single-tone snr/sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09636-018 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 11. AD9643-170 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12, f in2 = 92.12 mhz, f s = 170 msps
AD9643 rev. a | page 17 of 36 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09636-019 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 12. AD9643-170 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12, f in2 = 187.12 mhz, f s = 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 02 03 04 05 06 07 08 0 frequency (mhz) amplitude (dbfs) 09636-020 170msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 89dbc (96dbfs) figure 13. AD9643-170 two-tone fft with f in1 = 89.12, f in2 = 92.12 mhz, f s = 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 02 03 04 05 06 07 08 0 frequency (mhz) amplitude (dbfs) 09636-021 170msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 84dbc (91dbfs) figure 14. AD9643-170 two-tone fft with f in1 = 184.12, f in2 = 187.12 mhz, f s = 170 msps 100 95 90 85 80 75 70 130 140 150 160 120110100 90 807060 50 40 170 sample rate (msps) snr/sfdr (dbc and dbfs) 09636-022 sfdr, channel b snr, channel b sfdr, channel a snr, channel a figure 15. AD9643-170 single-tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 6000 5000 4000 3000 2000 1000 0 n + 2 n + 3 n + 4 n + 5 n + 1 n n ? 1 n ? 2 n ? 3 n ? 4 n ? 5 output code number of hits 09636-023 1.34lsb rms 16,379 total hits figure 16. AD9643-170 grounded input histogram 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 020304050607080 90 100 frequency (hz) amplitude (dbfs) 09636-024 210msps 90.1mhz @ ?1dbfs snr = 70.6db (71.6dbfs) sfdr = 88dbc figure 17. AD9643-210 single-tone fft with f in = 90.1 mhz
AD9643 rev. a | page 18 of 36 third harmonic second harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20304050607080 90 100 frequency (mhz) amplitude (dbfs) 09636-025 210msps 185.1mhz @ ?1dbfs snr = 70.3db (71.3dbfs) sfdr = 86dbc figure 18. AD9643-210 single-tone fft with f in = 185.1 mhz 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 020304050607080 90 100 frequency (mhz) amplitude (dbfs) 09636-026 210msps 305.1mhz @ ?1dbfs snr = 67.3db (68.3dbfs) sfdr = 75dbc figure 19. AD9643-210 single-tone fft with f in = 305.1 mhz 120 100 80 60 40 20 0 ?10 ?20?30 ?40?50?60?70?80?90?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09636-027 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 20. AD9643-210 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 90.1 mhz 100 95 90 85 80 75 70 65 60 snr/sfdr (dbc and dbfs) 09636-028 330 360 390 3002702402101801501209060 frequency (mhz) snr (dbfs) sfdr (dbc) figure 21. AD9643-210 single-tone snr/sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09636-029 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 22. AD9643-210 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12, f in2 = 92.12 mhz, f s = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09636-030 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 23. AD9643-210 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12, f in2 = 187.12 mhz, f s = 210 msps
AD9643 rev. a | page 19 of 36 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 020304050607080 90 100 frequency (mhz) amplitude (dbfs) 09636-031 210msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 88dbc (95dbfs) figure 24. AD9643-210 two-tone fft with f in1 = 89.12, f in2 = 92.12 mhz, f s = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 020304050607080 90 100 frequency (mhz) amplitude (dbfs) 09636-032 210msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 88dbc (95dbfs) figure 25. AD9643-210 two-tone fft with f in1 = 184.12, f in2 = 187.12 mhz, f s = 210 msps 100 95 90 85 80 75 70 140 160 120 100806040 180 200 sample rate (msps) snr/sfdr (dbc and dbfs) 09636-033 snr, channel b sfdr, channel b snr, channel a sfdr, channel a figure 26. AD9643-210 single-tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 n + 2 n + 3 n + 4 n + 5 n + 1 n n ? 1 n ? 2 n ? 3 n ? 4 n ? 5 output code number of hits 09636-034 1.44lsb rms 16,378 total hits figure 27. AD9643-210 grounded input histogram 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100110120 frequency (mhz) amplitude (dbfs) 09636-035 250msps 90.1mhz @ ?1dbfs snr = 70.6db (71.6dbfs) sfdr = 88dbc figure 28. AD9643-250 single-tone fft with f in = 90.1 mhz 0 ?20 third harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100110120 frequency (mhz) amplitude (dbfs) 09636-036 250msps 185.1mhz @ ?1dbfs snr = 70.6db (71.6dbfs) sfdr = 85dbc second harmonic figure 29. AD9643-250 single-tone fft with f in = 185.1 mhz
AD9643 rev. a | page 20 of 36 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 2030405060708090100110120 frequency (mhz) amplitude (dbfs) 09636-037 250msps 305.1mhz @ ?1dbfs snr = 68.6db (71.6dbfs) sfdr = 83dbc figure 30. AD9643-250 single-tone fft with f in = 305.1 mhz 120 100 80 60 40 20 0 ?10?20?30?40?50?60?70?80?90?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09636-038 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 31. AD9643-250 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz 100 95 90 85 80 75 70 65 60 240 260 220 2001801601401201008060 frequency (mhz) snr/sfdr (dbc and dbfs) 09636-039 snr (dbfs) sfdr (dbc) figure 32. AD9643-250 single-tone snr/sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09636-040 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 33. AD9643-250 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12, f in2 = 92.12 mhz, f s = 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09636-041 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 34. AD9643-250 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12, f in2 = 187.12 mhz, f s = 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 100 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09636-042 250msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 87dbc (94dbfs) figure 35. AD9643-250 two-tone fft with f in1 = 89.12, f in2 = 92.12 mhz, f s = 250 msps
AD9643 rev. a | page 21 of 36 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 100 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09636-043 250msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 87dbc (94dbfs) figure 36. AD9643-250 two-tone fft with f in1 = 184.12, f in2 = 187.12 mhz, f s = 250 msps 100 95 90 85 80 75 70 220200 180 160 140 12010080 60 40 240 sample rate (msps) snr/sfdr (dbc and dbfs) 09636-044 snr, channel b sfdr, channel b snr, channel a sfdr, channel a figure 37. AD9643-250 single-tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 n + 2 n + 3 n + 4 n + 5 n + 1 n n ? 1 n ? 2 n ? 3 n ? 4 n ? 5 output code number of hits 09636-045 1.33lsb rms 16,378 total hits figure 38. AD9643-250 grounded input histogram
AD9643 rev. a | page 22 of 36 equivalent circuits v in avdd 09636-006 figure 39. equivalent analog input circuit 0.9v 15k ? 15k ? c lk+ clk? avdd 09636-007 avdd avdd figure 40. equivalent clock lnput circuit 09636-063 d r v dd dataout+ v? v+ d a taout? v+ v? figure 41. equivalent lvds output circuit sdio 350 ? 26k ? drvdd 09636-009 figure 42. equivalent sdio circuit sclk or pdwn 350 ? 26k ? 09636-010 figure 43. equivalent sclk or pdwn input circuit csb or oeb 350 ? 26k ? a vdd 09636-011 figure 44. equivalent csb input circuit a vdd avdd 16k? 0.9v 0.9v sync 0 9636-012 figure 45. equivalent sync input circuit
AD9643 rev. a | page 23 of 36 theory of operation the AD9643 has two analog input channels and two digital output channels. the intermediate frequency (if) signal passes through several stages before appearing at the output port(s). the dual adc design can be used for diversity reception of signals, where the adcs operate identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample frequencies from dc to 300 mhz using appropriate low-pass or band-pass filtering at the adc inputs with little loss in adc performance. operation to 400 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. synchronization capability is provided to allow synchronized timing between multiple devices. programming and control of the AD9643 are accomplished using a 3-pin, spi-compatible serial interface. adc architecture the AD9643 architecture consists of a dual front-end sample- and-hold circuit, followed by a pipelined switched-capacitor adc. the quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor digital- to-analog converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the recon- structed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single- ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. during power-down, the output buffers go into a high impedance state. analog input considerations the analog input to the AD9643 is a differential switched- capacitor circuit that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in figure 46 ). when the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, the shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. refer to the an-742 application note , frequency domain response of switched-capacitor adcs ; the an-827 application note , a resonant approach to interfacing amplifiers to switched-capacitor adcs ; and the analog dialogue article, transformer-coupled front-end for wideband a/d converters , for more information on this subject. c par1 c par1 c par2 c par2 s s s s s s c fb c fb c s c s bias bias v in+ 09636-050 h v in? figure 46. switche d-capacitor input for best dynamic performance, the source impedances driving vin+ and vin? should be matched, and the inputs should be differentially balanced. input common mode the analog inputs of the AD9643 are not internally dc biased. in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum performance. an on-board common-mode voltage reference is included in the design and is available from the vcm pin. using the vcm output to set the input common mode is recommended. optimum performance is achieved when the common-mode voltage of the analog input is set by the vcm pin voltage (typically 0.5 avdd). the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. this decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor. differential input configurations optimum performance is achieved while driving the AD9643 in a differential input configuration. for baseband applications, the ad8138, ada4937-2 , ada4938-2 , and ada4930-2
AD9643 rev. a | page 24 of 36 differential drivers provide excellent performance and a flexible interface to the adc. the output common-mode voltage of the ada4930-2 is easily set with the vcm pin of the AD9643 (see figure 47 ), and the driver can be configured in a sallen-key filter topology to provide band-limiting of the input signal. v in 76.8 ? 120? 0.1f 200 ? 200? 90? 0.1f avdd 33 ? 33 ? 33 ? 15? 15? 5pf 15pf 15pf adc vin? vin+ vcm ada4930-2 09636-051 figure 47. differential input configuration using the ada4930-2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 48 . to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r3 r2 c2 09636-052 r3 0.1f 33 ? figure 48. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz. excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the AD9643. for applications where snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 50 ). in this configuration, the input is ac-coupled and the vcm voltage is provided to each input through a 33 resistor. these resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input fre- quency and source impedance. based on these parameters, the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. table 10 displays recommended values to set the rc network for different input frequency ranges. however, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. note that the values given in table 10 are for each r1, r2, c2, and r3 component shown in figure 48 and figure 50 . table 10. example rc network freuency range (m) r1 series () c1 differential (pf) r2 series () c2 shunt (pf) r3 shunt () 0 to 100 33 8.2 0 15 49.9 100 to 300 15 3.9 0 8.2 49.9 an alternative to using a transformer-coupled input at frequencies in the second nyquist zone is to use an amplifier with variable gain. the ad8375 or ad8376 digital variable gain amplifier (dvgas) provides good performance for driving the AD9643. figure 49 shows an example of the ad8376 driving the AD9643 through a band-pass antialiasing filter. ad8376 AD9643 1h 1h 1nf 1nf vpos vcm 15pf 68nh 2.5k ?U 2pf 301 ? 165 ? 165? 5.1pf 3.9pf 180nh 1000p f 1000pf notes 1. all inductors are coilcraft ? 0603cs components with the exception of the 1h choke inductors (coil craft 0603ls). 2. filter values shown are for a 20mhz bandwidth filter centered at 140mhz. 180nh 220nh 220nh 09636-054 figure 49. differential input configuration using the ad8376 adc r1 0.1f 0.1f 2 v p- p vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f c2 33? 33? s p a p 09636-053 r3 r3 0.1f 33? figure 50. differential double balun input configuration
AD9643 rev. a | page 25 of 36 voltage reference a stable and accurate voltage reference is built into the AD9643. the full-scale input range can be adjusted by varying the reference voltage via spi. the input span of the adc tracks reference voltage changes linearly. clock input considerations for optimum performance, the AD9643 sample clock inputs, clk+ and clk?, should be clocked with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or via capacitors. these pins are biased internally (see figure 51 ) and require no external bias. if the inputs are floated, the clk? pin is pulled low to prevent spurious clocking. 0 9636-055 avdd clk+ 4pf 4pf clk? 0.9v figure 51. simplified equivalent clock input circuit clock input options the AD9643 has a very flexible clock input structure. clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 52 and figure 53 show two preferable methods for clocking the AD9643 (at clock rates of up to 625 mhz). a low jitter clock source is converted from a single-ended signal to a differential signal using an rf balun or rf transformer. the rf balun configuration is recommended for clock frequencies between 125 mhz and 625 mhz, and the rf transformer is recom- mended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the AD9643 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9643 while preserving the fast rise and fall times of the signal, which are critical to low jitter performance. 390pf 390pf 390pf schottky diodes: hsms2822 cloc k input 50? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1z xfmr 0 9636-056 figure 52. transformer-coupled differential clock (up to 200 mhz) 390pf 390pf 390pf clock input 1nf 25? 25? clk? clk+ schottky diodes: hsms2822 adc 09636-057 figure 53. balun-coupled differential clock (up to 625 mhz) if a low jitter clock source is not available, another option is to ac-couple a differential pecl signal to the sample clock input pins as shown in figure 54 . the ad9510, ad9511 , ad9512, ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522, ad9523 , ad9524, and adclk905/adclk907/ adclk925 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? pecl driver 50k ? 50k ? clk? clk+ clock input clock input ad95xx adc 09636-058 figure 54. differential pecl sample clock (up to 625 mhz) a third option is to ac-couple a differential lvds signal to the sample clock input pins, as shown in figure 55 . the ad9510 , ad9511, ad9512 , ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522, ad9523 , and ad9524 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k ? 50k ? clk? clk+ clock input clock input ad95xx lvds driver adc 09636-059 figure 55. differential lvds sample clock (up to 625 mhz) input clock divider the AD9643 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. the duty cycle stabilizer (dcs) is enabled by default on power-up. the AD9643 clock divider can be synchronized using the external sync input. bit 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
AD9643 rev. a | page 26 of 36 clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9643 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9643. jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. the duty cycle control loop does not function for clock rates less than 40 mhz nominally. the loop has a time constant associated with it that must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calculated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ] )10/( lf snr ? in the equation, the rms aperture jitter represents the root- mean-square of all jitter sources, which include the clock input, the analog input signal, and the adc aperture jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 56 . 80 75 70 65 60 55 50 1 10 100 1000 input frequency (mhz) snr (dbc) 09636-060 0.05ps 0.2ps 0.5ps 1ps 1.5ps measured figure 56. AD9643-250 snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9643. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. refer to the an-501 application note , aperture uncertainty and adc system performance , and the an-756 application note , sampled systems and the effects of clock phase noise and jitter , for more information about jitter performance as it relates to adcs. power dissipation and standby mode as shown in figure 57 , the power dissipated by the AD9643 is proportional to its sample rate. the data in figure 57 was taken using the same operating conditions as those used for the typical performance characteristics section. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.5 0.4 0.3 0.2 0.1 0 0 40 60 80 100 120 140 160 180 200 220 240 encode frequency (msps) total power (w) supply current (a) 09636-061 total power i avdd i drvdd figure 57. AD9643-250 power and current vs. sample rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the AD9643 is placed in power-down mode. in this state, the adc typically dissipates 10 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the AD9643 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map register description section and the an-877 application note , interfacing to high speed adcs via spi , for additional details.
AD9643 rev. a | page 27 of 36 digital outputs the AD9643 output drivers can be configured for either ansi lvds or reduced drive lvds using a 1.8 v drvdd supply. as detailed in the an-877 application note , interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when using the spi control. digital output enable function (oeb) the AD9643 has a flexible three-state ability for the digital output pins. the three-state mode is enabled using the oeb pin or through the spi interface. if the oeb pin is low, the output data drivers are enabled. if the oeb pin is high, the output data drivers are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that oeb is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. when using the spi interface, the data outputs of each channel can be independently three-stated by using the output enable bar bit (bit 4) in register 0x14. because the output data is interleaved, if only one of the two channels is disabled, the output data of the remaining channel is repeated in both the rising and falling output clock cycles. timing the AD9643 provides latched data with a pipeline delay of 10 input sample clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. the length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9643. these transients can degrade converter dynamic performance. the lowest typical conversion rate of the AD9643 is 40 msps. at clock rates below 40 msps, dynamic performance may degrade. data clock output (dco) the AD9643 also provides data clock output (dco) intended for capturing the data in an external register. figure 2 shows a graphical timing diagram of the AD9643 output modes. table 11. output data format input (v) vin+ ? vin?, input span = 1.75 v p-p (v) offset binary output mode twos complement mode (default) or vin+ ? vin? +0.875 11 1111 1111 1111 01 1111 1111 1111 1
AD9643 rev. a | page 28 of 36 channel/chip synchronization the AD9643 has a sync input that allows the user flexible synchronization options for synchronizing the internal blocks. the sync feature is useful for guaranteeing synchronized operation across multiple adcs. the input clock divider can be synchronized using the sync input. the divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence by setting the appropriate bits in register 0x3a. the sync input is internally synchronized to the sample clock. however, to ensure that there is no timing uncertainty between multiple parts, the sync input signal should be synchronized to the input clock signal. the sync input should be driven using a single-ended cmos type signal. using bit 1 in register 0x59, the sync input can be set to either level or edge sensitive mode. if the sync input is set to edge sensitive mode, bit 0 of register 0x59 can be used to determine whether the rising or falling edge is used.
AD9643 rev. a | page 29 of 36 serial port interface (spi) the AD9643 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information, see the an-877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 12 ). the sclk (serial clock) pin is used to synchronize the read and write data presented from/to the adc. the sdio (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active low control that enables or disables the read and write cycles. table 12. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of csb, in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 58 and table 5 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and the w1 bits. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 12 comprise the physical interface between the user programming device and the serial port of the AD9643. the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enou gh to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an-812 application note , micro- controller-based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9643 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods.
AD9643 rev. a | page 30 of 36 spi accessible features table 13 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an-877 application note , interfacing to high speed adcs via spi . the AD9643 part-specific features are described in the memory map register description section. table 13. features accessible using the spi feature name description mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digita lly adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09636-062 figure 58. serial port interface timing diagram
AD9643 rev. a | page 31 of 36 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); and the adc functions registers, including setup, control, and test (address 0x08 to address 0x59). the memory map register table (see table 14 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x14, the output mode register, has a hexadecimal default value of 0x05. this means that bit 0 = 1 and bit 2 = 1, and the remaining bits are 0s. this setting is the default output format value, which is twos complement. for more information on this function and others, see the an-877 application note , interfacing to high speed adcs via spi . this document details the functions controlled by register 0x00 to register 0x25. the remaining registers, register 0x3a and register 0x59, are documented in the memory map register description section. open and reserved locations all address and bit locations that are not included in table 14 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the AD9643 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 14 . logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x20, address 0x3a, and address 0x59 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the internal update takes place when the transfer bit is set, and then the bit autoclears. channel-specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 14 as local. these local registers and bits can be accessed by setting the appropriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel a. registers and bits designated as global in table 14 affect the entire part and the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
AD9643 rev. a | page 32 of 36 memory map register table all address and bit locations that are not included in table 14 are not currently supported for this device. table 14. memory map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configurati on registers 0x00 spi port configuration (global) 1 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so that lsb first mode or msb first mode registers correctly, regardless of shift mode. 0x01 chip id (global) 8-bit chip id[7:0] (AD9643 = 0x82) (default) 0x82 read only. 0x02 chip grade (global) open open speed grade id 00 = 250 msps open open open open speed grade id used to differentiate devices; read only. channel index and transfer registers 0x05 channel index (global) open open open open open open adc b (default) adc a (default) 0x03 bits are set to determine which device on the chip receives the next write command; applies to local registers only. 0xff transfer (global) open open open open open open open transfer 0x00 synchro- nously transfers data from the master shift register to the slave. adc functions 0x08 power modes (local) open open external power- down pin function (local) 0 = power- down 1 = standby open open open internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = reserved 0x00 determines various generic modes of chip operation. 0x09 global clock (global) open open open ope n open open open duty cycle stabilizer (default) 0x01 0x0b clock divide (global) open open input clock di vider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 auto- matically cause the duty cycle stabilizer to become active.
AD9643 rev. a | page 33 of 36 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0d test mode (local) user test mode control 0 = con- tinuous/ repeat pattern 1 = single pattern, then 0s open reset pn long gen reset pn short gen output test mode 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn long sequence 0110 = pn short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x00 when this register is set, the test data is placed on the output pins in place of normal data. 0x0e bist enable (local) open open open open open reset bist sequence open bist enable 0x00 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to ?32 (twos complement format) 0x00 0x14 output mode open open open output enable bar (local) open output invert (local) 1 = normal (default) 0 = inverted output format 00 = offset binary 01 = twos complement (default) 10 = gray code 11 = reserved (local) 0x05 configures the outputs and the format of the data. 0x15 output adjust (global) open open open open lv ds output drive current adjust 0000 = 3.72 ma output drive current 0001 = 3.5 ma output drive current (default) 0010 = 3.30 ma output drive current 0011 = 2.96 ma output drive current 0100 = 2.82 ma output drive current 0101 = 2.57 ma output drive current 0110 = 2.27 ma output drive current 0111 = 2.0 ma output drive current (reduced range) 1000 to 1111 = reserved 0x01 0x16 clock phase control (global) invert dco clock open open open open ope n open open 0x00 0x17 dco output delay (global) enable dco clock delay open open dco clock delay [delay = (3100 ps regi ster value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps 11110 = 3100 ps 11111 = 3200 ps 0x00 0x18 input span select (global) open open open full-scale in put voltage selection 01111 = 2.087 v p-p 00001 = 1.772 v p-p 00000 = 1.75 v p-p (default) 11111 = 1.727 v p-p 10000 = 1.383 v p-p 0x00 full-scale input adjustment in 0.022 v steps. 0x19 user test pattern 1 lsb (global) user test pattern 1[7:0] 0x00 0x1a user test pattern 1 msb (global) user test pattern 1[15:8] 0x00 0x1b user test pattern 2 lsb (global) user test pattern 2[7:0] 0x00 0x1c user test pattern 2 msb (global) user test pattern 2[15:8] 0x00 0x1d user test pattern 3 lsb (global) user test pattern 3[7:0] 0x00 0x1e user test pattern 3 msb (global) user test pattern 3[15:8] 0x00
AD9643 rev. a | page 34 of 36 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x1f user test pattern 4 lsb (global) user test pattern 4[7:0] 0x00 0x20 user test pattern 4 msb (global) user test pattern 4[15:8] 0x00 0x24 bist signature lsb (local) bist signature[7:0] 0x00 read only. 0x25 bist signature msb (local) bist signature[15:8] 0x00 read only. 0x3a sync control (global) open open open open open clock divider next sync only clock divider sync enable master sync buffer enable 0x00 0x59 sync pin control (local) open open open open open open sync pin sensitivity 0 = sync on high level 1 = sync on edge sync pin edge sensitivity 0 = sync on falling edge 1 = sync on rising edge 0x00 1 the channel index register at address 0x05 should be set to 0x03 (default) when writing to address 0x00. memory map register description for more information on functions controlled in register 0x00 to register 0x25, see the an-877 application note , interfacing to high speed adcs via spi . sync control (register 0x3a) bits[7:3]reserved bit 2clock divider next sync only if the master sync buffer enable bit (address 0x3a, bit 0) and the clock divider sync enable bit (address 0x3a, bit 1) are high, bit 2 allows the clock divider to sync to the first sync pulse that it receives and to ignore the rest. the clock divider sync enable bit (address 0x3a, bit 1) resets after it syncs. bit 1clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0master sync buffer enable bit 0 must be set high to enable any of the sync functions. if the sync capability is not used, this bit should remain low to conserve power. sync pin control (register 0x59) bits [7:2]reserved bit 1sync pin sensitivity if bit 1 is set to 0, the sync input responds to a level. if this bit is set low, the sync input responds to the edge (rising or falling) set in bit 0 of address 0x59. bit 0sync pin edge sensitivity if bit 1 is set high, setting bit 0 to a 0 causes the sync input to respond to a falling edge. if this bit is set, the sync input respond to a rising edge.
AD9643 rev. a | page 35 of 36 applications information design guidelines before starting system level design and layout of the AD9643, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the AD9643, it is recommended that two separate 1.8 v supplies be used: one supply should be used for analog (avdd), and a separate supply should be used for the digital outputs (drvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. these capacitors should be located close to the point of entry at the pc board level and close to the pins of the part with minimal trace length. a single pcb ground plane should be sufficient when using the AD9643. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the AD9643 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about the packaging and pcb layout of chip scale packages, refer to the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 48 . for optimal channel-to-channel isolation, a 33 resistor should be included between the AD9643 vcm pin and the channel a analog input network connection, as well as between the AD9643 vcm pin and the channel b analog input network connection. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9643 to keep these signals from transitioning at the converter input pins during critical sampling periods.
AD9643 rev. a | page 36 of 36 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 59. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9643bcpz-170 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD9643bcpz-210 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD9643bcpz-250 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD9643bcpzrl7-170 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD9643bcpzrl7-210 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD9643bcpzrl7-250 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 AD9643-170ebz ?40c to +85c eval uation board with AD9643-170 AD9643-210ebz ?40c to +85c ev aluation board with AD9643-210 AD9643-250ebz ?40c to +85c eval uation board with AD9643-250 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09636-0-5/11(a)

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